Memory Module Simulation

I am having some trouble with my Verilog memory module simulation code. I have tried several different corrections, and it seems that it compiles fine. However, my simulation results are not what they should be. It doesn't look like the value is being stored in address and then sent to data_out, when it is supposed to. I am designing a RAM memory called MEM containing 256 words of 8 bits each.

module Memory(address, data_in, WE, RE, clk, data_out);

input WE, RE, clk;
input [7:0] data_in;
input [7:0] address;

output [7:0] data_out;

reg [7:0] data_out;

reg[7:0]mem[0:255];

always @(negedge clk)
begin
    if(WE==1 && RE==0)
        data_out <= mem[address];
    else if (RE==1 && WE==0)
        mem[address] <= data_in;
    else 
        data_out <= 4'bz;
end

endmodule

I am confident I am close to the right answer, but I think something minor is holding me back.