Going through my computer science and looking how the implementation of how cache works.
Why is it that we do not have 2+ L1 Cache, since the CPU is already able to determine that there is a hit / miss and then access the L2.
Wouldn't it be more efficient by added an extra bit to the tag that determines if it was a complete hit, add a multiplexer(mux) at the end of all the L1 cache system ?
This would reduce the complexity of a larger L1 cache and be cheaper to manufacture along with only increasing access time by around 20-30 ps.
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